Yusuf Leblebici - Publications#
Prof. Yusuf Leblebici has contributed extensively to education in Electronic Circuits and Systems through his book: “CMOS Digital Integrated Circuits: Analysis and Design” coauthored with Steve Kang and published by McGraw-Hill Publishers in five editions. Overall the book sold over 200’000 copies and was translated into Chinese and Greek. The sale volume of the textbook speaks for itself as worldwide reception. The book covers the very-large scale integration (VLSI) design principles, is self-contained, extremely clear and formative. It targets both advanced undergraduates and graduate students as well as the professional audience of electronic engineers in search for updates and/or retraining.
Moreover, his broad and impactful research activity is documented by many publications. Three areas of his work are highlighted next and the related publications.
Neuromorphic Circuits and Systems
Leblebici's research aims at exploiting intrinsic electrical characteristics of semiconductors and nanoelectronic devices, as well as analog circuits mimicking relevant natural characteristics or operation.
The past decade has witnessed an explosive growth of research as well as applied results exploiting artificial neural networks, an area which has remained relatively dormant for more than 30 years mainly due to the lack of sufficiently compact circuit implementations, and the limitations of effective training algorithms. During the 2010’s, especially assisted by the availability of big data for training purposes, this domain has experienced a strong resurgence, resulting in a multitude of very impressive applications. Newly emerging device technologies such as memristive elements and non-volatile memory arrays have also helped accelerate the developments.
Leblebici's research during the past one decade has mainly focused on this promising research area.
Concepts derived from artificial neural networks, and spiking neural networks were used to develop integrated computational systems, relying on novel nano-electronic components such as ReRAM and PCRAM arrays. Close collaboration with industrial partners have resulted in numerous novel solutions in circuit and system architectures, Memory-based computing and inference, as well as novel training algorithms and methods for improving the accuracy of such systems.
Noteworthy strong contributions:
İ. Boybat, M. Le Gallo, S. Nandakumar, T. Moraitis, T. Parnell et al. Neuromorphic computing with multi-memristive synapses, Nature Communications, vol. 9, article no. 2514, 2018. (DOI: 10.1038/s41467-018-04933-y)
A. Fumarola, S. Sidler, K. Moon, J. Jang, R. Shelby et al. Bidirectional Non-Filamentary RRAM as an Analog Neuromorphic Synapse, Part II, Impact of Al/Mo/Pr0.7Ca0.3MnO3 Device Characteristics on Neural Network Training Accuracy, IEEE Journal of Electron Devices Society, vol. 6, pp. 169-178, 2018. (DOI: 10.1109/JEDS.2017.2782184)
G. W. Burr, R. M. Shelby, A. Sebastian, S. Kim, S. Kim et al. Neuromorphic Computing Using Non-Volatile Memory, Advances in Physics, X, vol. 2, no. 1, pp. 89-124, 2017. (DOI: 10.1080/23746149.2016.1259585)
S. Wozniak, A. Pantazi, S. Sidler, N. Papandreou, Y. Leblebici et al. Neuromorphic Architecture with 1M Memristive Synapses for Detection of Weakly Correlated Inputs, IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 64, no. 11, pp. 1342-1346, 2017. (DOI: 10.1109/TCSII.2017.2697457)
High-Speed ADC Architectures
The design of very high-sampling-rate, energy efficient analog-digital converters (ADC) has always been one of the most challenging areas of integrated circuit engineering. The importance of high-speed ADCs has further increased with the rapid development of high data-rate wireline and wireless data links that rely on front-end conversion for effective DSP techniques, to achieve equalization and noise cancellation over non-ideal channels. The sampling rates required for such direct conversion tasks can easily exceed tens of GHz, with 6-to-8 bit accuracy, and under very limited energy budget. Typically, these ADCs will need to integrated in larger quantities on the interface (data TX/RX) circuitry to accommodate multiple channels. Therefore, a small footprint and compatibility with conventional digital CMOS technology are also required.
To answer these needs, a long-neglected ADC category, i.e., successive-approximation-register (SAR) ADC was successfully adapted to very high speed operation with multiple time-interleaved channels. The key advantages of SAR ADC architecture include a very small circuit area (allowing multiple identical time-interleaved channels to be placed side-by-side, in close proximity) and the fact that the circuit operation is almost exclusively relying on “digital” components, such as DFFs and logic gates. The first experimental circuits proved to be highly efficient, and this has spawned a whole family of ADCs that were remarkably successful in answering the demands of the new wireline data links. Many iterations of SAR ADC architectures based on 32nm SOI, 28nm FD-SOI, and 28nm bulk CMOS technologies were realized and experimentally demonstrated with impressive results. It is worth noting that the highest-sampling-speed 8 bit ADC was built and demonstrated by Lukas Kull (PhD graduate of Leblebici) in 2014, with a measured sampling rate of 90 GHz, and this record is yet to be broken, as of 2022. The following two publication describe this outstanding work.
L. Kull, J. Pliva, T. Toifl, M. Schmatz, P. A. Francese et al. Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs with Optimized Input Bandwidth in 32 nm CMOS, IEEE Journal of Solid-State Circuits, vol. 51, no. 3, pp. 636-648, 2016. (DOI: 10.1109/Jssc.2016.2519397)
L. Kull, T. Toifl, M. Schmatz, P. A. Francese, C. Menolfi et al. A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS, IEEE Journal of Solid State Circuits, vol. 48, no. 12, pp. 3049-3058, 2013. (DOI: 10.1109/JSSC.2013.2279571)
Ultra Low-Power Integrated Circuits
The demands for implementing ultra-low power / ultra-low energy digital circuits in future computing systems are increasingly pushing the design of logic circuits in sub-threshold regime as a very important challenge for next-generation nanometer-scale technologies. Here, the main goal is to overcome the limitations of leakage power/energy dissipation by operating the transistors in weak inversion regime. In sub-threshold MOS devices, current density is very low and the ratio of the transconductance to bias current of the device (gm/ID) is maximum. Meanwhile, the exponential relationship between drain current and gate voltage can make them very suitable for implementing widely adjustable circuits. CMOS logic circuits utilizing subthreshold-regime transistors can operate with very low power dissipation that is mainly due to the dynamic (switching) power consumption and is quadratically dependent to the supply voltage. Hence, reducing the supply voltage will result in reduction of power dissipation as well as the output logic swing. Supply voltage reduction, on the other hand, increases the delay in each gate which means the power dissipation, logic swing, and speed of operation are tightly related to each other.
Leblebici's outstanding result indicates that the operating current dissipation of logic cells can be reduced to levels as low as 1-10 pA, and that the power-delay product of a typical subthreshold source-coupled logic gate can be well below 1 fJ. This suggests that specific circuit topologies have a very significant potential for ultra low-power applications, especially in circuits where the operating (clock) speed can be reduced through parallelism, and where the energy supply is limited. The ability to de-couple the power dissipation from the output voltage swing also provides an additional degree of freedom when considering frequency-scaling techniques to match the operation speed of the circuit to available energy. This important area of research has highlights in the following contributions.
S. A. Tajalli, Y. Leblebici. Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL, IEEE Transactions on Circuits and Systems II, Express Briefs, vol. 59, no. 12, pp. 903-907, 2012. (DOI: 10.1109/Tcsii.2012.2231032)
A. Tajalli, M. Alioto and Y. Leblebici. Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits, IEEE Transaction on Circuits and Systems-II, vol. 56, no. 2, pp. 127-131, 2009. (DOI: 10.1109/TCSII.2008.2011603)
A. Tajalli, E. J. Brauer, Y. Leblebici and E. Vittoz. Subthreshold Source-Coupled Logic Circuits for Ultra Low Power Applications, IEEE Journal of Solid-State Circuits, vol. 43, no. 7, pp. 1699 - 1710, 2008. (DOI: 10.1109/JSSC.2008.922709)
